mp7616 1 rev. 2.00 features ? monolithic cmos construction ? full four-quadrant multiplication ? excellent stability over temperature and time ? ttl/5 v cmos compatible ? guaranteed monotonic 15 v cmos 16-bit multiplying digital-to-analog converter ? low sensitivity to output amplifier vos ? low glitch energy ? buffered version: mp7626 ? 5 v version: mp7616b general description the mp7616 is a high density 16-bit cmos multiplying digi- tal-to-analog converter. silicon nitride passivation and un- trimmed silicon chromium resistors have been combined to pro- vide long term stability and reliability. using the most significant bit (msb) segmentation technique, the mp7616 features 13-bit (0.012%) differential and 12-bit (0.01%) integral linearity. to achieve 13-bit linearity without laser trim, the mp7616 digi- tally decodes the four msb's into 15 equal current sources, rather than the standard binary-weighted sources. each resis- tor contributes only 1/16 full scale output thus reducing the matching accuracy requirement of the resistor and cmos switches from 0.0015% to 0.024%. the decoding technique achieves an eightfold improvement in differential linearity stability over temperature, an eightfold im- provement in relative accuracy due to aging effects (long term stability), a fourfold improvement in glitch amplitude, and a ten- fold reduction in sensitivity to output amplifier offset voltage. simplified block diagram 4 to 15 decoder r rrrrrrrrrrrrrr 12-bit dac msb 45 lsb to 12-bit dac to switches r fb i out2 i out1 v dd v ref gnd 1 16
mp7616 2 rev. 2.00 ordering information package type temperature range part no. ceramic dip mp7616jd ceramic dip MP7616KD ceramic dip mp7616td* plastic dip mp7616jn plastic dip mp7616kn 40 to +85 c 40 to +85 c 55 to +125 c 40 to +85 c 40 to +85 c + 14 + 14 + 7 + 7 + 7 + 16 + 16 + 8 + 8 + 8 + 0.8 + 0.8 + 0.8 + 0.8 + 0.8 soic mp7616js soic mp7616ks 40 to +85 c 40 to +85 c + 14 + 7 + 16 + 8 + 0.8 + 0.8 inl (lsb) dnl (lsb) gain error (% fsr) *contact factory for non-compliant military processing pin configuration 1 2 3 4 5 6 7 8 9 10 22 21 20 19 18 17 16 15 14 13 11 12 22 pin cdip, pdip (0.400o) d22, n22 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 2 bit 1 (msb) bit 16 (lsb) bit 15 bit 14 gnd i out2 i out1 r fb v ref v dd 24 pin soic (jedec, 0.300o) s24 bit 2 bit 1 (msb) bit 16 (lsb) bit 15 bit 14 gnd i out2 i out1 r fb v ref v dd bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 24 1 13 12 2 3 4 5 6 7 15 14 17 16 8 9 19 18 10 11 23 22 21 20 n/c n/c see packaging section for package dimensions 1 n/c no connection 1 2 bit 3 data input bit 3 2 3 bit 4 data input bit 4 3 4 bit 5 data input bit 5 4 5 bit 6 data input bit 6 5 6 bit 7 data input bit 7 6 7 bit 8 data input bit 8 7 8 bit 9 data input bit 9 8 9 bit 10 data input bit 10 9 10 bit 11 data input bit 11 10 11 bit 12 data input bit 12 11 12 bit 13 data input bit 13 pin out definitions dip name description 13 n/c no connection 12 14 bit 14 data input bit 14 13 15 bit 15 data input bit 15 14 16 bit 16 data input bit 16 (lsb) 15 17 v dd positive power supply 16 18 v ref reference input voltage 17 19 r fb internal feedback resistor 18 20 i out1 current output 1 19 21 i out2 current output 2 20 22 gnd ground 21 23 bit 1 data input bit 1 (msb) 22 24 bit 2 data input bit 2 soic dip name description soic
mp7616 3 rev. 2.00 electrical characteristics (v dd = + 15 v, v ref = +10 v unless otherwise noted) 25 c tmin to tmax parameter symbol min typ max min max units test conditions/comments static performance 1 fsr = full scale range resolution (all grades) n 16 16 bits integral non-linearity 5 inl lsb best fit straight line spec. (relative accuracy) (max inl min inl) / 2 j+ 14 + 14 k, t + 7+ 7 differential non-linearity 5 dnl lsb j+ 16 + 16 k, t + 8+ 8 gain error ge + 0.8 % fsr using internal r fb gain temperature coefficient 2 tc ge + 2.0 ppm/ c d gain/ d temperature non-linearity tempco 2 + 0.5 ppm/ c differential linearity tempco 2 + 0.5 ppm/ c power supply rejection ratio psrr + 5+ 50 + 50 ppm/% |d gain/ d v dd | d v dd = + 5% output leakage current 6 i out + 1+ 10 + 200 na dynamic performance 2 current settling time t s 2 m s to 0.01% of fsr; all digital inputs low to high and high to low feedthrough at i out1 f t 1 2 mv p-p v ref = 10khz, 20 vp-p reference input input resistance r in 1310 1 10k w digital inputs 3 logical a1o voltage v ih 3.0 2.4 3.0 v logical a0o voltage v il 0.8 0.8 v input leakage current i lkg + 1.0 + 1.0 m a analog outputs 2 output capacitance c out1 100 pf dac inputs all 1's c out1 50 pf dac inputs all 0's c out2 50 pf dac inputs all 1's c out2 100 pf dac inputs all 0's power supply 4 functional voltage range 2 v dd 4.5 15 16 4.5 16 v supply current i dd 0.4 4 4 ma all digital inputs = 0 v or all = 5 v
mp7616 4 rev. 2.00 electrical characteristics (cont'd) notes: specifications are subject to change without notice 1 full scale range (fsr) is 10v for unipolar mode. 2 guaranteed but not production tested. 3 digital input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur. 4 specified values guarantee functionality. refer to other parameters for accuracy. 5 linearity error is degraded by 65 m v for every mv of voltage offset at output amplifier. 6 output leakage current refers to i out1 . one lsb of current constantly flows into i out2 (30na at 5k w input impedance, v ref = +10 v) due to ladder termination into i out2 . absolute maximum ratings (t a = +25 c unless otherwise noted) 1, 2 v dd to gnd 0 to +17 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . digital input voltage to gnd gnd 0.5 to v dd +0.5 v . . . . i out1 , i out2 to gnd gnd 0.5 to v dd +0.5 v . . . . . . . . . . . v ref to gnd + 25 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v rfb to gnd + 25 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature 65 c to +150 c . . . . . . . . . . . . . . . . . lead temperature (soldering, 10 seconds) +300 c . . . . . . package power dissipation rating to 75 c cdip, pdip, soic 1000mw . . . . . . . . . . . . . . . . . . . . . . . . derates above 75 c 13mw/ c . . . . . . . . . . . . . . . . . . . . . notes: 1 stresses above those listed under aabsolute maximum ratingso may cause permanent damage to the device. this is a stress rating only and functional operation at or above this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. 2 any input pin which can see a value outside the absolute maximum ratings should be protected by schottky diode clamps (hp5082-2835) from input pin to the supplies. application notes refer to section 8 for applications information
mp7616 5 rev. 2.00 a .225 5.72 b 0.014 0.023 0.356 0.584 b 1 0.038 0.065 0.965 1.65 2 c 0.008 0.015 0.203 0.381 d 1.111 28.22 4 e 0.350 0.410 8.89 10.41 4 e 1 0.390 0.420 9.91 10.67 7 e 0.100 bsc 2.54 bsc 5 l 0.125 0.200 3.18 5.08 l 1 0.150 3.81 q 0.015 0.070 0.381 1.78 3 s 0.080 2.03 6 s 1 0.005 0.13 6 a 0 15 0 15 d b e 22 lead ceramic dual-in-line (400 mil cdip) d22 symbol min max min max notes inches millimeters s notes 1. index area; a notch or a lead one identification mark is located adjacent to lead one and is within the shaded area shown. 2. the minimum limit for dimension b 1 may be 0.023 (0.58 mm) for all four corner leads only. 3. dimension q shall be measured from the seating plane to the base plane. 4. this dimension allows for off-center lid, meniscus and glass overrun. 5. the basic lead spacing is 0.100 inch (2.54 mm) be- tween centerlines. 6. applies to all four corners. 7. this is measured to outside of lead, not center. 22 111 12 see note 1 e a c e 1 l q seating plane base plane l 1 a s 1 b 1
mp7616 6 rev. 2.00 22 lead plastic dual-in-line (400 mil pdip) n22 22 1 12 11 d eb 1 a 1 e 1 a c e a l b q 1 seating plane symbol min max min max inches a 0.225 5.72 a 1 0.015 0.38 b 0.014 0.023 0.356 0.584 b 1 (1) 0.038 0.065 0.965 1.65 c 0.008 0.015 0.203 0.381 d 1.050 1.110 26.67 28.19 e 0.385 0.425 9.78 10.80 e 1 0.330 0.380 8.38 9.65 e 0.100 bsc 2.54 bsc l 0.115 0.150 2.92 3.81 a 0 15 0 15 q 1 0.055 0.070 1.40 1.78 s 0.040 0.080 1.02 2.03 millimeters note: (1) the minimum limit for dimensions b1 may be 0.023o (0.58 mm) for all four corner leads only. s
mp7616 7 rev. 2.00 symbol min max min max a 0.097 0.104 2.464 2.642 a1 0.0050 0.0115 0.127 0.292 b 0.014 0.019 0.356 0.483 c 0.0091 0.0125 0.231 0.318 d 0.602 0.612 15.29 15.54 e 0.292 0.299 7.42 7.59 e 0.050 bsc 1.27 bsc h 0.400 0.410 10.16 10.41 h 0.010 0.016 0.254 0.406 l 0.016 0.035 0.406 0.889 a 0 8 0 8 inches millimeters 24 lead small outline (300 mil jedec soic) s24 e d e h b a l c a 1 seating plane a h x 45 24 13 12
mp7616 8 rev. 2.00 notice exar corporation reserves the right to make changes to the products contained in this publication in order to im- prove design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits de- scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contains here in are only for illustration purposes and may vary depending upon a user's specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circum- stances. copyright exar corporation datasheet april 1995 reproduction, in part or whole, without the prior written consent of exar corporation is prohibited.
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